rev 2.2, august 1, 2010 page 1 of 10 400 west cesar chavez, austin, tx 78701 1+(512) 416 - 85 00 1+(512) 416 - 9669 www.silabs.com SL16020DC key features ? low power dissipation - 14 .5 ma - typ cl=15pf - 20 .0ma - max cl=15p f ? 3.3v +/ - 10% power supply range ? 27.000mhz crystal or clock input ? 27.000mhz refclk ? 100mhz ssclk with ssel0/1 spread options ? low ccj jitter ? low lt ji tter ? internal voltage regulators ? 45% to 55% output duty cycle ? on - chip crystal oscillator ? - 10 to +85 temperature range ? 10- pin 3x3x0.75 mm tdfn package application ? video cards ? nb and dt pcs ? hdtv and dvd - r/w ? routers, switches and servers ? data communications ? embeded digital applications description the sl16020 dc is a low power dissipation spread spectrum clock generator using sli propri etary low jitter pll. the sl1602 0 dc provides two output clocks. refclk (pin - 9) which is a buffered output of the 27.000mhz input crystal and ssclk (pin - 5) which is synthesized as 100.000mhz nominal by an internal pll using the 27.00mhz external input crystal or clock . in addition, ssel0 (pin - 7) and ssel1 (pin - 3) spread percent selection control inputs enable users to select fr om 0.0% (no sprea d) to ? 1.5 % down spread at 100.000mhz ssclk output to reduce and optimize system emi levels. the sl16020 dc operates in an extended temperature range of - 10 to +85c. contact sli for other programmable frequencies, spread spectrum clock (ss c) options, as well as 2.5v+/ - 10 and 1.8v+/ - 5% power supply options. benefits ? emi reduction ? improved jitter ? low power dissipation ? eleminates external xtals or xos block diagram 1 low jitter pll with modulation control 5 input decoder 4 6 10 7 3 300k ssclk 100.000mhz with spread options xin/clkin xout vdd1 vss1 ssel0 ssel1 9 refclk 27.000mhz 8 2 vss2 vdd2 figure 1. block diagram low jitter and power clock generator with sscg
rev 2.2, august 1, 2010 page 2 of 10 SL16020DC pin configuration 10 9 8 7 1 2 3 4 xout refclk vdd2 ssel0 xin/clkin vss2 ssel1 vdd1 ssclk 5 6 vss1 figure 2. 10 - pin tdfn (3x3x0.75 mm) table 1. pin description pin number pin name pin type pin description 1 xin input external crystal or clock input. capacitance at this pin is 4 pf - typ . 2 vss2 power power supply g round for 27.000mhz refclk output. 3 ssel1 input ssel1 spread percent selection pin. refer to table 5 for available spread options using ssel1 pin . this pin has 150k pull down resistor to vss . 4 vdd1 power positive power supply for 100.000mhz ssclk output. 3.3v +/ -10%. 5 ssclk output ssclk clock output. 100. 000mhz nominal. refer to table 5 for available spread % options by using ssel0 and ssel1 control pins. 6 vss1 power power supply ground for 100.000mhz ssclk output. 7 ssel0 input ssel spread percent selection pin. refer to table 5 for available spread options using ssel0 pin . this pin has 150k pull down resistor to vss . 8 vdd2 power positive power supply f or 27.000mhz refclk output. 3.3v +/ -10%. 9 refclk output refclk clock output. 27.000mhz nominal. 10 xout output crystal o utput. capacitance at this pin 4 pf - typ . if clock input is used, leave this pin unconnected (n/c).
rev 2.2, august 1, 2010 page 3 of 10 SL16020DC table 2. absolute maximum rati ngs description condition min max unit supply voltage, vdd - 0.5 4.2 v all inputs and outputs - 0.5 vdd+0.5 v ambient operating temperature in operation, extended c grade -10 85 c storage temperature no power is applied -65 150 c junction temperatu re in operation, power is applied - 125 c soldering temperature - 260 c esd rating (human body model) jedec22 - a114d - 4,000 4,000 v esd rating (charge device model) jedec22 - c101c - 1,500 1,500 v esd rating (machine model) jedec22 - a115d -200 200 v ta ble 3. dc electrical characteristics (c - grade) unless otherwise stated vdd= 3.3v+/ - 10%, cl=15pf and ambient temperature range - 10 to +85deg c description symbol condition min typ max unit operating voltage vdd1/2 vdd1=vdd2=3.3v +/ - 10% 2.97 3.3 3.63 v input low voltage vinl ssel0 and ssel1 0 - 0.2 v input middle voltage vinm ssel0 and ssel1 0.4vdd - 0.6vdd input high voltage vinh ssel0 and ssel1 0.9vdd - vdd v output low voltage vol iol=15ma, pins 5 and 9 - - 0.4 v output high voltage voh ioh= - 15ma , pins 5 and 9 vdd - 0.4 - - v power supply current idd ssel=1, m or 0, cl=15pf, vdd=3.63v and t=85c - 14.5 20.0 ma input capacitance cin1 xin and xout, pins 1 and 10 - 4 - pf input capacitance cin2 ssel0/1, pins 7 and 3 - 3 5 pf load capacitance cl ssclk and refclk, pins 5 and 9 - - 15 pf pull down resistor r pd pins 3 and 7 100 150 250 k
rev 2.2, august 1, 2010 page 4 of 10 SL16020DC table 4. ac electrical characteristics (c - grade) unless otherwise stated vdd= 3.3v+/ - 10%, cl=15pf and ambient temperature range - 10 to +85 deg c paramete r symbol condition min typ max unit frequency range fr -1 input crystal or clock range, +/ - 10 ppm accuracy if a crystal is used - 27.000 - mhz frequency range fr -2 refclk, pin 9 - 27.000 - mhz frequency range fr -3 ssclk, pin 5 - 100.000 - mhz frequency accuracy facc1 refclk, pin 9 - +/ -0 - ppm frequency accuracy facc2 ssclk, pin 5, ssel0/1=0 - +/ -0 - ppm rise and fall time tr/f -1 refclk, pin 9, cl=5pf, measured from 20% to 80% of vdd - 1.0 1.5 ns rise and fall time tr/f -2 refclk, pin 9, cl=15pf, measu red from 20% to 80% of vdd - 1.5 2.0 ns rise and fall time tr/f -3 ssclk, pin 5, cl=5pf, measured from 20% to 80% of vdd - 0.75 1.0 ns rise and fall time tr/f -4 ssclk, pin 5, cl=15pf, measured from 20% to 80% of vdd - 1.5 1.75 ns output duty cycle dc ssc lk and refclk , pins 5 and 9 measured at vdd/2, cl=15pf 45 50 55 % cycle -to - cycle jitter ccj 1 ssclk, pin 5, all s0/1 states -100 +/ -50 1 00 ps cycle -to - cycle jitter ccj2 refclk, pins 9, all s0/1 states -150 +/ -100 150 ps long term jitter ltj refclk, pi ns 9, 10,000 cycles , all s0/1 states - 150 250 ps power - up time (vdd) tpu1 time from 0.9vdd to valid frequency at output pins 5 and 9 - 2.0 5.0 ms spread percent change settling time tss% time from ssel0/1 change to stable ssclk with spread % - - 1.0 ms modulation frequency mf ssclk, 100mhz nominal, pin 5 31 32 33 khz modulation type and slew rate fmtsr ssclk, pin 5, triangular modulation profile - - 0.125 %/s
rev 2.2, august 1, 2010 page 5 of 10 SL16020DC table 5. ssel1 and ssel0 versus spread % selection at ssclk ssel1 (pin 3) ssel0 (pin 7) spread percent (%) ssclk (pin 5) low (vss) low (vss) spread off (no spread) low (vss) middle (vdd/2) - 0.50 % low (vss) high (vdd ) - 0. 375 % middle (vdd/2) l ow (vss) - 0.25 % middle (vdd/2) middle (vdd/2) - 0.75 % middle (vdd/2) high (vdd ) - 1.00 % high (vdd) low (vss) - 1.50 % high (vdd ) middle (vdd/2) spread off (no spread )- test high (vdd ) high (vdd ) spread off (no spread ) - test table 6. recommended crystal specifications description min typ max unit nominal frequency (fundamental crystal) - 27.000 - mhz crystal accuracy - +/ - 10 - ppm load capacitance 6 12 18 pf shunt capacitance - - 7.0 pf equivalent series resistance (esr) - - 30 drive level - - 1.0 mw
rev 2.2, august 1, 2010 page 6 of 10 SL16020DC external resistor dividers for 3 - level logic implementation 3-level logic high=vdd vdd 5k ssel0 or ssel1 input 7/3 3-level logic low=vss vss 5k ssel0 or ssel1 input 7/3 high (h) = vdd middle (m) = vdd/2 low (l) = vss 3-level logic middle=vdd/2 vss vdd 5k 5k ssel0 or ssel1 input 7/3 figure 3. fsel0 and fsel1 spread % selection logic note: ssel0 a nd ssel1 pins use 3 - level l(low) = vss , m(middle)=vdd/2 and h(high) = vdd 3 - level logic to provide 9 spread % values at s sclk (pin 5) as given in table 5 . use 5k /5k external resistor dividers at ssel0 and ssel1 pins from vdd to vss to obtain vdd/2 for m =vdd/2 logic level as shown above in figure 3 .
rev 2.2, august 1, 2010 page 7 of 10 SL16020DC external co mponents and design considerations typical application circuit SL16020DC xin(1 ) vdd2(8) xout(10) ssclk(5 ) ssel1(3) ssel0(7) 100mhz 27mhz cl1 cl2 0.1 f vss2(2) refclk(9) 27mhz vss1(6) vdd1( 4) 10f external crystal and crystal load capacitors required if crystal is used. if external clock (xo) is used leave pin-10 xout unconnected (n/c) and drive pin 1 xin/clkin with clock vdd vdd 0.1f 5k 5k this example is configured for -0.5% spread ssel0=m (vdd /2) and ssel1=low ( vss) 5k figure 4. typical application schematic comments and recommendations crystal and crystal load: only use a parallel resonant fundamental at cut crystal. do not us e higher overtone crystals. to meet the crystal initial accuracy specification (in ppm) make sure that external crystal load capacitor is matched to crystal load specification. to determine the value of cl1 and cl2, use the following formula; c1 = c2 = 2 cl ? (cpin + cp) where: cl is load capacitance stated by crystal manufacturer cpin is the sl16010 pin capacitance (4pf) cp is the parasitic capacitance of the pcb traces. example; if a crystal with cl=12pf specification is used and cp=1pf (parasitic pcb capacitance on pcb), 19 or 20pf external capacitors from pins xin (pin - 1) and xout (pin - 10) to vss are required since cxin=cxout=4pf for the sl1610dc product. users must verify cp value. decoupling capacitor: a decoupling ca s d f l w r u r i ) p x v w e h x v h g e h w z h h q 9 ' ' s l q v d q g 9 6 6 s l q 3 o d f h the capacitor on the component side of the pcb as close to the vdd1/2 pins as possible. the pcb trace to the vdd1/2 pins and to the vss via should be kept as short as possible do not u se vias between the decoupling capacitor and the vdd1/2 pins. in addition, a 10uf capacitor should be placed between vdd and vss. series termination resistor : a series termination resistor is recommended if the distance between the outputs (refclk and ssc lk) and the load if pcb trace is over 1 ? inch. the nominal impedance of the outputs is about 24
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rev 2.2, august 1, 2010 page 8 of 10 SL16020DC to the clock outputs as possible. package o utline and package dimensions 10- pin tdfn package (3x3x0.75 mm) 3.00+/-0.10 0.20+/-0.025 c: 0.25x45 c pin #1 id top view bottom view side view side view 0.00-0. 05 0.50 3.00+/-0.10 0.75+/-0.05 0 0.25+/-0.05 2.00+/- 0.10 0.30+/-0.05 1.50+/-0.10 dimentions are in mm 1 5 6 10 table 7. thermal characteristics parameter symbol condition min typ max unit thermal resistance junction to ambient ja1 still air - 75 - c/w ja2 1m/s a ir flow - 70 - c/w ja3 3m/s air flow - 55 - c/w thermal resistance junction to case jc independent of air flow - 25 - c/w
rev 2.2, august 1, 2010 page 9 of 10 SL16020DC table 8. ordering information note: 1. SL16020DC is rohs compliant and halogen free. product revisions history revision date originator description rev 1.0 11/12 /2009 c . ozdalga original rev 1.1 11/12/20 09 c. ozdalga change spread % from - 1.50% to - 0.375% for s1=0 (vss) and s0=1(vdd) state on table 5. rev 1.2 11/23/2009 c. ozdalga add 150k weak pull down resistors at s0 and s1 pins to vss. rev2.0 4/19/2010 c. ozdalga final datasheet after product qualification. ccj1 ssclk decreased to +/ - 50- ps - typ and +/ - 100ps - max and ccj2 refclk decreased to +/ - 100ps - typ and +/ - 150ps - max and ltj decreas ed to +/ - 250ps - max. idd change to 20ma - max (amd spec 50ma - max). rev 2.1 6/14/2010 c. ozdalga add clock input function (in addition to crystal). SL16020DC works with both external crystal and clock (xo). rev 2.2 8/1/2010 c. ozdalga add ?halogen free?, pag e 8. ordering number marking shipping package package temperature sl16020 dc sl16020 dc tube 10-p in tdfn - 10 to 85c sl16020 dct sl16020 dc tape and reel 10- pin tdfn - 10 to 85c
rev 2.2, august 1, 2010 page 10 of 10 SL16020DC the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions , and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories assume any liability arising out of t he application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applicat ions intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products fo r any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.
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